1. Field of the Invention
This invention relates to a photoresist stripping solution and a method of stripping photoresists using the same. The invention is suitable for use in the fabrication of semiconductor devices such as ICs and LSIs, as well as liquid-crystal panel apparatus.
2. Description of Relevant Art
The fabrication of semiconductor devices such as ICs and LSIs, as well as liquid-crystal panel apparatus, comprises forming a uniform photoresist coating over conductive metallic layers, insulation layers such as an SiO2 film formed on a substrate (silicon wafer) by CVD; performing selective exposure and development to form a photoresist pattern; selectively etching the substrate having the conductive metallic layers, the insulation layers formed thereon by CVD, using the photoresist pattern as a mask to thereby form a microcircuit; and then removing the unwanted photoresist layer with a stripping solution.
With the recent tendency toward highly integrated, high-density circuits, dry etching enabling fine etching with a higher density has become the major means. Also, it has been a practice to employ plasma ashing to remove the unnecessary photoresist layers remaining after etching. After these etching and ashing treatments, residues comprising modified photoresist films and other components, referred to horn-like shaped “veil”, “fences” or “side-walls”, remain on the bottom or side wall of patterned grooves. In addition, etching of metallic layers and ashing treatment builds up metal depositions. Such post-ashing residues or depositions should be completely stripped away so as to keep good yields in the production of semiconductors.
In particular, as the degree of integration of semiconductor devices increases and the chip size decreases, efforts are recently being made to reduce the feature size of wiring circuits while fabricating them in an increasing number of superposed layers. A problem with this approach is that wiring delay is caused by the resistance of the metal films used (wiring resistance) and wiring capacity. To deal with this problem, it has been proposed to use metals such as copper (Cu) that have smaller resistance than aluminum (Al) mainly used as a conventional wiring material, and recent models of semiconductor devices can be divided into two types, one using Al conductors (Al, Al alloy and other Al-based metal wiring) and the other using Cu conductors (Cu-based metal wiring). In addition to the need to prevent devices of these two types from corroding, it is also necessary to provide effective protection against corrosion of other metals on the devices, and further improvements are desired to achieve effective stripping away of the photoresist layer and the post-ashing residues, and to prevent metal conductors from corroding.
For critical reasons such as low etching resistance of copper, copper metal wiring is generally formed by the dual damascene process. While various methods have been proposed to implement the dual damascene process, one example comprises the following: a Cu layer is formed on a substrate; a multiple of interlevel films, such as low-dielectric films (e.g. SOG film) and insulation films (e.g. SiN film and SiO2 film), are superposed on the Cu layer; a photoresist layer is provided on the topmost layer, and selectively exposed and developed to form a photoresist pattern; with this photoresist pattern used as a mask, the low-dielectric films, insulation films are etched and subjected to ashing treatment to strip away the photoresist pattern while forming via holes that connect to the Cu layer on the substrate; subsequently, another photoresist layer is formed on the topmost of the remaining superposed interlevel films and is selectively exposed and developed to form a new photoresist pattern; with this photoresist pattern used as a mask, a specified number of low-dielectric films, insulation films are etched, and subjected to ashing treatment to strip away the photoresist pattern while forming wiring grooves (trenches) that communicate with the above-described via holes; the via holes and wiring trenches are filled with Cu by plating or other method, thereby forming multiple layers of Cu wiring.
In the dual damascene process, Cu-based residues (Cu deposition) are prone to occur as the result of etching and ashing treatments that are effected to form the via holes; in addition, Si-based residues (Si deposition) originating from the low-dielectric films and insulation films are prone to occur as the result of etching and ashing treatments that are effected to form the wiring trenches, and the residues are occasionally formed as Si deposition around the opening of each trench. Unless the Cu and Si depositions are completely stripped away, problems will occur such as lower yield of semiconductor fabrication.
Needless to say, the occurrence of Si-based residues (Si deposition) originating from the low-dielectric films and insulation films is not limited to the case of using the dual damascene process; they can occur in almost all cases of forming metal wiring on the substrate having. Si-based interlevel films thereon.
Thus, in the current photolithographic technology, the photoresist stripping techniques are required to meet increasingly rigorous conditions in order to adjust for the decreasing feature size of patterns, the formation of more interlevel layers on the substrate and the changes in materials formed on the substrate surface. Of course, to ensure a good working environment, the photoresist stripping solution to be used must be not only easy to handle but also less hazardous in such terms as toxicity and explosiveness.
Under these circumstances, a variety of stripping solutions based on quaternary ammonium hydroxides and water-soluble amines have been proposed to date as candidates that meet the above-mentioned various requirements of stripping photoresists and post-ashing residues (see, for example, JP-A-1-502059, JP-A-6-202345, JP-A-7-28254, JP-A-7-219241, JP-A-8-262746, JP-A-10-289891, JP-A-11-251214, JP-A-2000-164597 and JP-A-2001-22096).
A problem with the stripping solutions proposed in those patents is that if their ability to strip the photoresist film and post-ashing residues, particularly the ability to strip Si-based residues, is enhanced to an adequate level, they are not capable of providing adequate protection against corrosion of the Si substrate, particularly its reverse side; hence, the ability to strip the Si-based residues must be compromised to some extent.
However, for successful lithography in today's practice of fabricating semiconductor devices with an ever decreasing feature size and an increasing number of interlevel films superposed on the substrate, stripping of the Si-based residues cannot be compromised and it is desired to develop a stripping solution that meets both requirements for efficient stripping of Si-based residues and effective protection of the Si substrate from corroding.
A group of stripping solutions that contain hydroxylamines have also been proposed, but the starting materials from which they are made are highly hazardous (e.g. explosive) and at the stage of purification, they are not easy to handle since they are toxic or hazardous.